This disclosure relates to data processing.
Data transfer protocols can regulate the operation of data transfers between devices or nodes connected to one another via interconnect circuitry, for example in the context of a system on chip (SoC) or network on chip (NoC) system. An example of such a data transfer protocol is the so-called AMBA (Advanced Microcontroller Bus Architecture) CHI (Coherent Hub Interface) protocol.
In the CHI protocol, nodes can be categorised as request nodes (RN), home nodes (HN) or slave nodes (SN). Nodes can be fully coherent or input/output (I/O) coherent. A fully coherent HN or RN (HN-F, RN-F respectively) includes coherent cache storage; a fully coherent SN (SN-F) is paired with an HN-F. An HN-F can manage coherency for a memory region.
Here, the term “coherent” implies that that data written to a memory address in the coherent memory system by one node is consistent with data read from that memory address in the coherent memory system by another of the nodes. A role of logic associated with the coherence function is therefore to ensure that before a data handling transaction takes place, if the version of the data item to be accessed is out of date (because of a modification made to another copy of the same data item), the copy to be accessed is first brought up to date. Similarly, if the data handling transaction involves modifying a data item, then coherence logic avoids conflicts with other existing copies of the data item.
The CHI protocol aims to avoid the interconnect becoming a bottleneck inhibiting data transfers, by providing that a write data channel should be free-flowing. This is achieved in CHI-compliant systems by the HN allocating a full packet buffer to an RN in response to receiving a write request from that RN relating to a data write to an SN. The packet buffer is released when all of the data flits (flow control digits) relevant to the transfer have been received from the RN and sent on to the SN. This arrangement brings significant requirements for buffer space at the HN.
Other example protocols include the AXI (Advanced Extensible Interface) or ACE (AXI Coherency Extensions) protocols. In some respects the CHI and AXI/ACE protocols are incompatible. The ACE protocol does not make use of a HN for example, but does provide coherency. While each requires that write data is free-flowing, the interconnect (which manages coherency in the ACE protocol) must route write data as part of the same transaction as a write request.